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Under MIL. STD.883e 3015.7 Is there any ‘implied’ allowance to condition pins during HBM ESD zap based on ‘unique’ analog circuit functionality? Intuitively it doesn’t make sense, but there may be a practical side...any thoughts or experience? Anonymous, South Portland, Maine

I asked a colleague, Mike Hopkins from KeyTek, and his reply is no, there are no conditioning requirements for devices under the HBM testing found in either ESD Association or JEDEC standards. There is, however, a conditioning requirement in the JEDEC standard 78 for conditioning devices for Latch-up Testing.

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